System requirements needed to interact with and visualize large, time-dependent data sets include a large, high-bandwidth disk array to store the entire data set being processed, a high speed network to download a problem set, a large, high-speed memory to buffer all data required to process a single simulation time step, computational power that is adequate to manipulate, enhance, and visualize the data sets, and a real-time, high resolution visual display. Furthermore, it is important that these functions be provided within a highly programmable and flexible user environment.
To realize such large and complex systems a multiprocessor approach may be taken, wherein a plurality of data processors operate in parallel on the same aspect or on different aspects of a processing task.
However, one problem that is encountered in multiprocessor systems is the implementation of diagnostic and control circuitry for the plurality of processors. In this regard, it is known in the art to provide a diagnostic bus, which may be bit serial in nature, that is independent of other system buses. Through the use of the diagnostic bus an external device is enabled to read out system information and to stimulate system components to perform operational diagnostics.
The following U.S. Patents teach aspects of conventional data processing system diagnostic circuitry and/or the use of a bit serial bus for communicating between various system components.
In U.S. Pat. No. 4,409,656, issued Oct. 11, 1983, entitled "Serial Data Bus Communication System" to Andersen et al. there is described a serial data bus architecture for use in a system having a plurality of user computers. The serial data bus functions to permit two-way, point-to-point communication between any pair of user computers or, alternatively, to permit any one user computer to broadcast simultaneously to all other users in the system, via a central bus arbiter. A two wire serial channel is employed, with one wire for control and one for data. Multiple redundancy is also provided so that there are several possible serial paths between any two end points.
U.S. Pat. No. 4,527,237, issued Jul. 2, 1985, entitled "Data Processing System" to Frieder et al. shows in FIG. 14 a remote diagnostic interface and a console interface, both of which are connected to dual serial channels. The system also includes a diagnostic bus interface connected to a diagnostic bus.
In U.S. Pat. No. 4,701,845, issued Oct. 20, 1987, entitled "User Interface Processor for Computer Network with Maintenance and Programmable Interrupt Capability" to Andreasen et al. there is described a user interface processor that supports a computer system network having a central processing unit connected to remote peripherals through data link processors. The user interface processor, or maintenance processor, connects to a central host processing unit through a processor interface card which attaches directly to the host system bus.
In commonly assigned U.S. Pat. No. 4,312,066, issued Jan. 19, 1982, entitled "Diagnostic/Debug Machine Architecture" to Bantz et al. there is described a diagnostic and debugging facility said to be specifically designed and intended for use with a host computer embodying a Level Sensitive Scan Design (LSSD) concept. As disclosed in Col. 5, lines 45-60, the LSSD provides a shift-register capability to every logic system latch in a processing unit and organizes the shift-register latches into one or more shift-register data channels having terminal stages accessible via an interface.
What is not taught by these U.S. Patents, and what is thus one object of the invention to provide, is a single wire bit serial diagnostic bus for use by a Serial Diagnostic Interface (SDI) master in issuing information packets to SDI slaves.
A further object of the invention is to provide method and apparatus for use in a multiprocessor system for enabling one or more processors to be halted, a local memory of each of the processors to be modified, and the processors restarted.
A further object of the invention is to provide at each node of a multiprocessor system a diagnostic interface including registers and a controller coupled to a diagnostic bus for receiving diagnostic functions therefrom and for executing the functions, the functions enabling a local processor to be halted and its functionality simulated by the diagnostic interface.